Many forms of comparator circuits are generally known in the art for comparing an input signal to a reference signal to produce an output signal indicative of some predetermined relationship therebetween. Applications for comparator circuits include level detectors, multivibrators, line receivers, sense amplifiers, phase locked loop circuits and pulse generators. Generally, these comparison circuits comprise a differential amplifier circuit wherein a reference potential is applied at one input thereof and an input signal is applied to the other input. A particular kind of load circuitry is connected to the differential amplifier circuit for producing the output signal when the input signal obtains a predetermined relationship with respect to the reference signal. For example, U.S. Pat. No. 3,872,323 to Thomas M. Frederiksen et al., issued Mar. 18, 1975, discloses a comparison circuit comprising such a differential amplifier and a differential to single ended converter circuit which is exemplary of the prior art. U.S. Pat. No. 4,717,839 to Applicant, issued Jan. 5, 1988, discloses a comparator circuit having improvements over the Frederiksen et al. patent.
However, it is well known in the semiconductor industry that the final cost of a monolithic integrated circuit is a function of the complexity and the number of process steps involved in manufacturing the device It is therefore desirable to take advantage of as simple as a process as possible, such as a single metal layer P-well process. Previously known CMOS comparators generally require a high input offset voltage and have a slow input to output response time It is also known that NPN transistors, as used in the above referenced issued patents, have higher transconductance, a lower offset voltage, better matching characteristics, and smaller area requirements than the N-channel transistor.
Thus, what is needed is a differential to single ended comparator manufactured with a CMOS process utilizing parasitic bipolar transistors and having a high transconductance, a low offset voltage, a low input to output response time, small physical area, improved matching characteristics, and reduced complexity and number of process steps involved in manufacturing the device.